RISC-V Technologies
Home
> RISC-V Technologies
> RISC-V
CPU
IPs
> RISC-V 32-bit Architecture IPs
>
E302A
E302A
RISC-V 32-bit Architecture IPs
E302A:
ESWIN Computing E302A 32-bit functional-safety processor is a 32-bit RISC-V automotive grade CPU IP product with low power consumption and ultra-small area.
It has functional Safety mechanism added such as, Parity/ECC, SPM (Stack Pointer Monitor) to meet ASIL-B functional safety standards.
To ease user RTL simulation debugging, it provides an ESWIN Sight function to let users easily probe the internal state and events of the CPU.
It has functional Safety mechanism added such as, Parity/ECC, SPM (Stack Pointer Monitor) to meet ASIL-B functional safety standards.
To ease user RTL simulation debugging, it provides an ESWIN Sight function to let users easily probe the internal state and events of the CPU.
Features
| Features | Description | ||||
| ISA | RISC-V 32-bit EMZc_Zicsr_Zifencei | ||||
| Modes | Machine-mode, User-mode | ||||
| Security | PMP Region can optional from 0 to 16 | ||||
| Pipeline | 3-stage pipeline | ||||
| TIM | TIM0 and TIM1, with configurable sizes from 0KB to 1286MB, ECC optional | ||||
| Interrupt | CLIC interrupt controller, supports 112 interrupt requests and non-maskable interrupt(NMI) | ||||
| Debug | Debug module, supports JTAG/cJTAG | ||||
| Bus Interface | 1. Peripheral Port: 32-bit AHB master interface 2. Front port: 32-bit AHB slave interface, used for external access to TIM0 and TIM1 |
||||
| CoreMark（CoreMarks/MHz） | 3.25 | ||||
| Dhrystone-Legla（DMIPS/MHz） | 1.47 | ||||
京公網(wǎng)安備 11030102011303號